Ram မ်ားႏွင့္ မိတ္ဆက္ျခင္း

SDRAM ေလးပါ

/CS	/RAS	/CAS	/WE	BAn	A10	An	Command
H	x	x	x	x	x	x	Command inhibit (No operation)
L	H	H	H	x	x	x	No operation
L	H	H	L	x	x	x	Burst Terminate: stop a burst read or burst write in progress.
L	H	L	H	bank	L	column	Read: Read a burst of data from the currently active row.
L	H	L	H	bank	H	column	Read with auto precharge: As above, and precharge (close row) when done.
L	H	L	L	bank	L	column	Write: Write a burst of data to the currently active row.
L	H	L	L	bank	H	column	Write with auto precharge: As above, and precharge (close row) when done.
L	L	H	H	bank	row		Active (activate): open a row for Read and Write commands.
L	L	H	L	bank	L	x	Precharge: Deactivate (close) the current row of selected bank.
L	L	H	L	x	H	x	Precharge all: Deactivate (close) the current row of all banks.
L	L	L	H	x	x	x	Auto refresh: Refresh one row of each bank, using an internal counter. All banks must be precharged.
L	L	L	L	0 0	mode		Load mode register: A0 through A9 are loaded to configure the DRAM chip. The most significant settings are CAS latency (2 or 3 cycles) and burst length (1, 2, 4 or 8 cycles)

DDR SDRAM ေလးပါ

 

Standard name	Memory clock (MHz)	Cycle time[4] (ns)	I/O bus clock (MHz)	Data rate (MT/s)	VDDQ (V)	Module name	Peak transfer rate (MB/s)	Timings (CL-tRCD-tRP)
DDR-200	100	10	100	200	2.5±0.2	PC-1600	1600
DDR-266	133⅓	7.5	133⅓	266⅔		PC-2100	2133⅓	2.5-3-3
DDR-333	166⅔	6	166⅔	333⅓		PC-2700	2666⅔
DDR-400A DDR-400B DDR-400C	200	5	200	400	2.6±0.1	PC-3200	3200	2.5-3-3 3-3-3 3-4-4

								Mobile DDR ေလးပါ CK CA0 (RAS) CA1 (CAS) CA2 (WE) CA3 CA4 CA5 CA6 CA7 CA8 CA9 Operation ↑ H H H — NOP ↓ — ↑ H H L H H — Precharge all banks ↓ — ↑ H H L H L — BA2 BA1 BA0 Precharge one bank ↓ — ↑ H H L H A30 A31 A32 BA2 BA1 BA0 Preactive (LPDDR2-N only) ↓ A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 ↑ H H L L — Burst terminate ↓ — ↑ H L H reserved C1 C2 BA2 BA1 BA0 Read (AP=auto-precharge) ↓ AP C3 C4 C5 C6 C7 C8 C9 C10 C11 ↑ H L L reserved C1 C2 BA2 BA1 BA0 Write (AP=auto-precharge) ↓ AP C3 C4 C5 C6 C7 C8 C9 C10 C11 ↑ L H R8 R9 R10 R11 R12 BA2 BA1 BA0 Activate (R0–14=Row address) ↓ R0 R1 R2 R3 R4 R5 R6 R7 R13 R14 ↑ L H A15 A16 A17 A18 A19 BA2 BA1 BA0 Activate (LPDDR2-N only) ↓ A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 ↑ L L H H — Refresh all banks (LPDDR2-Sx only) ↓ — ↑ L L H L — Refresh one bank (Round-robin addressing) ↓ — ↑ L L L H MA0 MA1 MA2 MA3 MA4 MA5 Mode register read (MA0–7=Address) ↓ MA6 MA7 — ↑ L L L L MA0 MA1 MA2 MA3 MA4 MA5 Mode register write (OP0–7=Data)     ↓ MA6 MA7 OP0 OP1 OP2 OP3 OP4 OP5 OP6 OP7
								DDR2 SDRAM ေလးပါ
								Standard name Memory clock (MHz) Cycle time (ns) I/O bus clock (MHz) Data rate (MT/s) Module name Peak transfer rate (MB/s) Timings[2][3](CL-tRCD-tRP) CAS latency(ns) DDR2-400B DDR2-400C 100 10 200 400 PC2-3200 3200 3-3-3 4-4-4 15   20   DDR2-533B DDR2-533C 133⅓ 7½ 266⅔ 533⅓ PC2-4200* 4266⅔ 3-3-3 4-4-4 11¼ 15   DDR2-667C DDR2-667D 166⅔ 6 333⅓ 666⅔ PC2-5300* 5333⅓ 4-4-4 5-5-5 12   15   DDR2-800C DDR2-800D DDR2-800E 200 5 400 800 PC2-6400 6400 4-4-4 5-5-5 6-6-6 10   12½ 15   DDR2-1066E DDR2-1066F 266⅔ 3¾ 533⅓ 1066⅔ PC2-8500* 8533⅓ 6-6-6 7-7-7 11¼ 13⅛                                                                                                                                        DDR3 SDRAM ေလးပါ                       Standard name Memory clock (MHz) Cycle time (ns) I/O bus clock (MHz) Data rate (MT/s) Module name Peak transfer rate (MB/s) Timings (CL-tRCD-tRP) CAS latency (ns) DDR3-800D DDR3-800E 100 10 400 800 PC3-6400 6400 5-5-5 6-6-6 12 1⁄2 15   DDR3-1066E DDR3-1066F DDR3-1066G 133⅓ 7 1⁄2 533⅓ 1066⅔ PC3-8500 8533⅓ 6-6-6 7-7-7 8-8-8 11 1⁄4 13 1⁄8 15   DDR3-1333F* DDR3-1333G DDR3-1333H DDR3-1333J* 166⅔ 6 666⅔ 1333⅓ PC3-10600 10666⅔ 7-7-7 8-8-8 9-9-9 10-10-10 10 1⁄2 12   13 1⁄2 15   DDR3-1600G* DDR3-1600H DDR3-1600J DDR3-1600K 200 5 800 1600 PC3-12800 12800 8-8-8 9-9-9 10-10-10 11-11-11 10   11 1⁄4 12 1⁄2 13 3⁄4 DDR3-1866J* DDR3-1866K DDR3-1866L DDR3-1866M* 233⅓ 4 2⁄7 933⅓ 1866⅔ PC3-14900 14933⅓ 10-10-10 11-11-11 12-12-12 13-13-13 10 5⁄7  11 11⁄14 12 6⁄7  13 13⁄14 DDR3-2133K* DDR3-2133L DDR3-2133M DDR3-2133N* 266⅔ 3 3⁄4 1066⅔ 2133⅓ PC3-17000 17066⅔ 11-11-11 12-12-12 13-13-13 14-14-14 10 5⁄16 11 1⁄4 12 3⁄16 13 1⁄8                                                                      DDR4 SDRAM ေလးပါ                     S BGn, BAn /ACT A17 A16 /RAS A15 /CAS A14 /WE A13 A12 A11 A10 A9–0 Command H — x — Deselect (No operation) L bank L Row address Active (activate): open a row L x H x H H H — x — No operation L x H x H H L x long x ZQ Calibration L bank H x H L H x BC x AP Column Read (BC=burst chop) L bank H x H L L x BC x AP Column Write (AP=auto-precharge) L x H x L H H — x — (Unassigned, reserved) L x H x L H L x H x Precharge all banks L bank H x L H L x L x Precharge one bank L x H x L L H — x — Refresh L register H 0 L L L 0 data Mode register set (MR0–MR6)

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